Noesis Technologies ntE1_G704 and ntT1_G704 IP cores implement ITU G.704/G.706 compliant framer/deframer functions for use in 2.048 Mbps and 1.544 Mbps TDM systems correspondingly. The functional features of our E1 and T1 framer/deframer solutions are based on the Dallas DS2180A and DS2181A chips. Programs written for these chips can be used with the core with only minor changes.

Our ntHDLC core implements a single-channel controller for the High-Level Data Link Control (HDLC) protocol and can be used used for public networks employing the X.25 communications protocol as well as in ISDN applications.

Our ntI2C_S Bus Controller provides a serial interface that meets the Philips I2C bus specification. The core supports all slave transfer modes to and from the I2C bus.
Networking IP Cores
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