Speech compression technology is widely used in digital communication systems such as wireless systems, VoIP, and video conference technology. Speech compression reduces data redundancy and thus eases bandwidth requirements.
The G.729 codec is standardized by International Telecommunication Union (ITU-T) and belongs to the category of Code-Excited Linear Prediction (CELP) speech coders and it compresses speech from 16 bit, 8 kHz samples (128 kbps) to 8 kbps. It is one of the most popular voice compression algorithms used in VoIP. G.729 is a loosy compression algorithm, i.e. the output speech is not identical to the input speech. The standard describes several variations. The G.729 AnnexA (G.729A) is the most H/W implementation attractive version since it is fully compatible with G.729 but exhibits lower computational complexity with acceptable quality. Noesis Technologies ntG729 core implements a multi-channel ITU G.729A voice codec and provides significant benefits in terms of cost and performance when compared with conventional DSP processor software implementation.
Noesis Technologies ntAPDCM core implements an area optimized ITU G.726/G.727 (40, 32, 24 and 16 kbps) compliant voice codec. It supports up to 64 full duplex or 128 half duplex channels with variable on-the-fly compression rate and a-law/u-law code selection.
Our ntG711_CMP and ntG711_EXP implement the ITU G.711 (64 kbps) compliant voice compressing and expanding functions correspondingly for a-law and u-law codes.
The fundamental principle of the CVSD algorithm is the encoding of one bit per sample. For example an audio signal sampled at 32 KHz will be compressed to 32 Kbps. The ntCVSD codec IP core can be configured to operate either as an encoder or as a decoder functional block. In encoder mode the core accepts input data at a rate of 8 KHz/128 Kbps or 16KHz/256Kbps and are sampled when the data strobe signal is asserted high. Higher input sampling data rates can also be supported with no up-sampling provision.
Noesis Technologies ntHUFF compression engine implements Huffman block differential compression algorithm. The core processes data blocks of 500 16-bit input samples “on the fly” with latency as little as 4 clock cycles. The worst case processing delay of the Huffman processor is 4175 clock cycles, which translates to a minimum data throughput rate of 106,8 Mbps assuming a 62.5 MHz system clock operating frequency. The core is ideal for use in applications like wireless sensor networks as well as any other application with slow changing nature of data, to fully benefit from the differential nature of the algorithm.
Source Coding IP Cores