ntBFFT core is a fully configurable solution that performs the FFT and IFFT transform. It is on-the-fly programmable in terms of transform size and type. It supports complex input/output and the results are output in normal order. The core uses fixed-point 2’s complement arithmetic with internal auto scaling to avoid arithmetic overflow and simplify dynamic range management. The ntBFFT core supports both radix2 & radix4 decimation in frequency algorithms. The ntBFFT uses a butterfly sequential architecture that provides balanced performance and silicon resources requirements. The implementation is portable to various silicon technologies, with a simple interface for easy integration in SoC applications.
•  Fully configurable, FFT/IFFT core.
•  Programmable transform type.
•  Programmable transform size from 8-points to 8K points.
•  16-bit complex I/O in 2's complement format.
•  Internally generated twiddle factors.
•  Supports radix2 and radix4 architecture.
•  Output in natural order.
•  Fully synchronous design.
•  Silicon proven in ASIC and FPGA technologies for a variety of applications.
The ntBFFT core can be used in a variety of applications, including:

• Communication Systems.
• Spectrum Analysis.
• OFDM Modems.
• Image Processing.
• Defense Receivers and Signal Monitoring.
• Medical and Scientific Instruments.
Block Diagram
Technical support by phone or email is included. First year of maintenance is also included. Additional support and annual maintenance options are available.
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntBFFT core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:

•  RMM compliant synthesizable VHDL or Verilog source code or FPGA netlist.
•  VHDL or Verilog test benches and example configuration files.
•  Matlab model.
•  Comprehensive technical documentation.
•  Technical support.
Implementantion Results
The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements.
Silicon Vendor Device FFT size/radix Resources Fmax
128/radix2 554 CLB Slices/4 Block RAMs 77 MHz
512/radix2 662 CLB Slices/4 Block RAMs 73 MHz
Xilinx Spartan3 1024/radix2 749 CLB Slices/4 Block RAMs 79 MHz
2048/radix2 1147 CLB Slices/8 Block RAMs 71 MHz
1024/radix4 1246 CLB Slices/4 Block RAMs 88 MHz
FFT version Description Latency
ntBFFT/radix2 Radix2 Sequential Block FFT Nlog2N
ntBFFT/radix4 Radix4 Sequential Block FFT Nlog4N
Silicon Vendor Device FFT size/radix Resources Fmax
128/radix2 245 CLB Slices/4 Block RAMs 161 MHz
512/radix2 272 CLB Slices/4 Block RAMs 162 MHz
Xilinx Virtex5 1024/radix2 289 CLB Slices/4 Block RAMs 159 MHz
2048/radix2 394 CLB Slices/8 Block RAMs 147 MHz
1024/radix4 539 CLB Slices/4 Block RAMs 146 MHz
Silicon Vendor Device FFT size/radix Resources Fmax
128/radix2 642 ALUTs/8 M9Ks 129 MHz
512/radix2 681 ALUTs/9 M9Ks 146 MHz
Altera Stratix3 1024/radix2 740 ALUTs/9 M9Ks 142 MHz
2048/radix2 1214 ALUTs/17 M9Ks 138 MHz
1024/radix4 1599 ALUTs/9 M9Ks 187 MHz
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